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asix electronics corporation 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http://www.asix.com.tw AX88871AP 10/100base dual speed bripeater controller asix asix AX88871AP 10/100base dual speed ? bripeater ? controller data sheets (08/11/ ? 99) document no . : ax871a-05.doc this data sheets contain new products information. asix electronics reserves the rights to modify the products specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. always contact asix for possible updates before starting a design.
AX88871AP bripeater asix electronics corporation 2 contents 1.0 ax88871a overview ................................ ................................ ................................ ................................ ..... 4 1.1 g eneral d escription ................................ ................................ ................................ ................................ ...... 4 1.2 f eatures ................................ ................................ ................................ ................................ .......................... 5 1.3 b lock d iagram ................................ ................................ ................................ ................................ ............... 6 1.4 p in c onnection d iagram ( mode 0) ................................ ................................ ................................ ................. 7 1.5 p in c onnection d iagram ( mode 1) ................................ ................................ ................................ ................. 8 2.0 pin description ................................ ................................ ................................ ................................ ........... 9 2.1 mii interfaces ................................ ................................ ................................ ................................ ................ 9 2.2 e xpansion b us i nterface for 100 m bps ................................ ................................ ................................ ....... 10 2.3 led d isplay ................................ ................................ ................................ ................................ .................. 11 2.4 b uffer memory pins group ................................ ................................ ................................ ........................... 12 2.5 m iscellaneous ................................ ................................ ................................ ................................ .............. 13 2.6 p ower on configuration setup signals cross reference table ................................ ................................ 14 3.0 functional description ................................ ................................ ................................ ..................... 15 3.1 r epeater s tate m achine ................................ ................................ ................................ .............................. 16 3.2 rxe /txe control ................................ ................................ ................................ ................................ .. 16 3.3 j abber s tate m achine ................................ ................................ ................................ ................................ .. 17 3.4 p artition s tate m achine ................................ ................................ ................................ ............................. 17 3.5 e xpansion l ogic (c ascade i nterface ) ................................ ................................ ................................ ......... 17 3.6 d ata f low control ................................ ................................ ................................ ................................ ...... 17 3.7 rid r eceive -t ransmit i nterface (d aisy c hain l ogic ) ................................ ................................ ............... 18 3.8 led d isplay i nterface ................................ ................................ ................................ ................................ 18 4.0 internal registers ................................ ................................ ................................ ................................ 20 4.1 c onfiguration r egister (config) ................................ ................................ ................................ ............. 20 4.2 r epeater id r egister ................................ ................................ ................................ ................................ ... 20 5.0 electrical specification and timing ................................ ................................ .......................... 21 5.1 a bsolute m aximum r atings ................................ ................................ ................................ ........................ 21 5.2 g eneral o peration c onditions ................................ ................................ ................................ ................... 21 5.3 dc c haracteristics ................................ ................................ ................................ ................................ ..... 21 5.4 ac specifications ................................ ................................ ................................ ................................ ......... 22 5.4.1 mii interface timing tx & rx ................................ ................................ ................................ ................. 22 5.4.2 expansion bus ................................ ................................ ................................ ................................ ......... 23 5.4.3 sram read cycle and write cycle ................................ ................................ ................................ ............. 24 5.4.4 led display ................................ ................................ ................................ ................................ ......... 25 5.4.5 led display after reset ................................ ................................ ................................ ......................... 25 5.4.6 repeater id daisy chain ................................ ................................ ................................ ......................... 26 6.0 package information ................................ ................................ ................................ ........................... 27 appendix a: applications ................................ ................................ ................................ .......................... 28 a.1 s tand - along 8- ports 10/100m bps hub a pplication ................................ ................................ ................. 28 a.2 m ultiple s tand - along hub c ascade a pplication ( old stack scheme ) ................................ .................. 28 a.3 m ultiple s tand - along hub c ascade a pplication (n ew stack scheme ) ................................ ................. 29 appendix b: using mii i/f connects to mac ................................ ................................ ...................... 30
AX88871AP bripeater asix electronics corporation 3 figures f ig - 1 c hip b lock d iagram ................................ ................................ ................................ ................................ ..... 6 f ig - 2 p in c onnection d iagram for mode 0 ................................ ................................ ................................ ........... 7 f ig - 3 p in c onnection d iagram for mode 1 ................................ ................................ ................................ ........... 8 f ig - 4 f unctional b lock d iagram ................................ ................................ ................................ ....................... 15 f ig - 5 a pplication for led display ................................ ................................ ................................ ..................... 19 f ig - 6 s tand - along 8- ports 10/100m bps hub a pplication ................................ ................................ ................ 28 f ig - 7 m ultiple s tand - along hub c ascade a pplication with old cascade method ................................ ....... 28 f ig - 8 m ultiple s tand - along hub c ascade a pplication with new cascade method ................................ ...... 29
AX88871AP bripeater asix electronics corporation 4 1.0 ax88871a overview the ax88871a 10/100mbps dual speed ? bripeater ? controller is ? a dual speed repeater with build in bridge function ? it is design for low cost dumb hub application. the ax88871a directly supports up-to eight 10/100mbps automatic links mii interfaces. maximum up-to 192 ports can be constructed when using inter-repeater bus horizontally cascades 4 ax88871a and vertically cascades 6 repeaters. when using the legacy method, maximum up-to 64 ports can be constructed when using expansion bus cascades 8 ax88871as. the ax88871a is designed base on ieee 802.3u clause 27 ? repeater for 100mb/s base-band networks ? it is fully compatible with ieee 802.3u standard. all of the asix repeater products with the same speeds has the same cascade methodology. so the ax88871a can cascade with ax88850, ax88860 and ax88870 series chips. that is asix maintain the consistency of the cascade method for all the repeater product line. 1.1 general description the ax88871a repeater controller is a subset of a repeater set containing all the repeater-specific components and functions, exclusive of phy components and functions. the ax88871a has only media independent interface (mii) to connect to phy devices. other then ax88850 series chips that has 2 kinds of interfaces. there are physical coding sub-layer (pcs) interface and media independent interface (mii). the ax88871a supports 8 mii interfaces ports, a bridge packet buffer sram interface, a 100mbps port expansion interface and led display interface. the ax88871a supports stand along 10/100mbps dual speed repeater applications. also it can expand the ports count via cascade to other ax88850 and ax88860 pure 100mbps repeater chips . . the ax88871a has two application mode. mode 0 single chip repeater application. mode 1 multiple chips cascaded repeater application.
AX88871AP bripeater asix electronics corporation 5 1.2 features ieee 802.3u repeater compatible supports per port 10/100mbps alternative with auto detected build in 10/100mbps bridge engine with following features 1. minimum 32k bytes, maximum 256k bytes sram to buffer packets 2. seamless buffer management without waste any space of buffer memory 3. simple asynchronous 8-bit sram interface to reduce system cost 4. 256 or 1024 entries is supported 5. auto learning and filtering 6. two forwarding modes are supported : store-n-forward and fragment-free 7. flow-control is supported optionally. 8. buffer ram auto testing 9. routing and learning at wire speed (148810 packets/sec at 100mbps) supports 8 10/100mbps network connections 8 dedicated mii interfaces can support 100base-tx/t4/fx phy interfaces port 7 and/or 8 can connect to bridge, switch or mac type device optionally. up-to 8 repeater chips can be cascaded for large hub application(old method) up-to 6 repeaters can be cascaded for vertical expansion(new feature) up-to 4 chips can be cascaded locally for horizontal expansion(new feature) support two application mode : single or cascade low latency design supports class ii repeater implementation with large port number all ports can be separately isolated or partitioned in response to fault condition separate jabber and partition state machines for each port per-port led display for jabber, partition, activity. global partition, ram test fail and collision, utilization (%) for 10/100mbps presentation power on led diagnosis. all the led display will follow the ? on-off-on-off-normal ? operation procedure during/after power on reset 208-pin pqfp
AX88871AP bripeater asix electronics corporation 6 1.3 block diagram 10/100 q-phy 10/100 q-phy mii i/f mii interface re-concilia- tion sub-layer (port 1 - port 7 ) speed detection circuit elasticity buffer for 100mbps and 10mbps mux repeater state machine of 100mbps collision handling logic for 100mbps and10mbps per port jabber ctl, auto-partition sm & per port collision , partition counters. registers mib i/f (reserved) cascade arbitration logic of 100mbps ........ mii i/f repeater state machine of 10mbps 100mbps to 10mbps bridge mem i/f (reserved) fig - 1 chip block diagram
AX88871AP bripeater asix electronics corporation 7 1.4 pin connection diagram (mode 0) fig - 2 pin connection diagram for mode 0 note : power on configuration setup signals refer section 2.6 cross referance table bma[12] bma[0] txen[6] txer[5] rxer[4] txd[3][1] rxd[3][2] rxdv[2] vdd vss lclk vdd 166 186 190 200 123 118 122 143 140 149 78 70 64 54 41 32 24 12 8 bma[9] bma[4] txd[7][1] rxd[6][1] txen[5] rxd[5][1] crs[4] txen[3] rxd[2][3] txer[0] vss vss vss1 171 174 192 203 206 117 151 148 75 57 42 26 31 21 bma[1] rxclk[7] rxd[5][2] txd[4][3] rxd[3][3] rxdv[3] txer[2] crs[2] rxd[1][1] rxd[1][0] txd[1][0] 165 207 145 107 105 83 66 65 63 60 25 16 13 3 7 bma[5] bmd[3] rxd[6][2] txd[3][3] rxd[2][0] rxd[1][3] crs[1] rxd[0][0] vdd vss vdd1 159 187 195 196 197 131 128 115 112 134 61 33 bma[7] txd[7][2] rxd[7][0] rxd[6][0] crs[3] txd[0][0] vdd 170 198 111 132 139 136 156 154 99 91 43 19 15 4 bma[11] bma[14] bma[15] /half10 rxd[7][2] crs[7] rxclk[6] txd[5][3] rxd[5][3] txd[2][3] rxd[0][3] vss1 vdd1 vss 157 162 178 204 109 106 104 101 82 81 77 62 11 6 bma[8] bmd[4] rxd[7][3] txd[6][3] txd[5][1] rxd[4][3] txd[2][2] rxd[0][2] test vss 208 142 155 147 94 89 71 49 17 txer[7] txer[6] rxclk[5] txen[4] txd[3][2] txer[3] txd[1][2] vdd1 176 144 138 95 90 68 58 56 55 45 23 bma[2] rxdv[7] rxer[6] rxd[5][0] txd[5][2] txd[4][1] txd[2][0] rxdv[1] 53 161 163 184 194 116 113 59 36 34 1 txd[6][1] txer[4] rxclk[3] rxd[3][0] rxd[1][2] txd[0][2] vdd 164 168 181 124 108 87 rxdv[6] crs[6] rxd[4][2] rxdv[4] rxd[3][1] rxer[3] rxclk[2] rxer[1] txd[1][3] txd[1][1] txen[1] rxclk[0] /bma[15] 167 172 130 141 100 98 85 28 22 9 bma[10] bma[3] bmd[1] rxd[7][1] crs[5] rxd[4][0] rxclk[4] rxd[2][2] txen[2] rxer[0] txen[0] vss vss1 vss /rst vss 175 183 185 193 126 119 110 121 137 135 152 153 79 74 bma[16] bmd[5] col_o[7] txd[7][0] txd[5][0] txd[0][1] crs[0] vdd vdd1 169 188 202 93 80 72 46 29 52 10 /bmwr bma[6] rxer[2] rxclk[1] txd[0][3] vss1 158 177 150 146 103 67 44 39 27 51 5 bmd[0] bmd[2] txen[7] col_o[6] txd[6][2] rxdv[5] 182 199 201 127 125 120 114 92 73 69 38 48 bma[13] bmd[7] txd[7][3] txd[6][0] rxd[6][3] rxer[5] txd[3][0] vss vdd 180 189 205 76 47 35 30 20 2 bma[17] bmd[6] rxer[7] txd[4][2] rxd[4][1] txd[4][0] txd[2][1] rxd[2][1] txer[1] rxdv[0] rxd[0][1] 160 173 179 191 129 133 102 97 88 86 84 40 37 50 18 14 AX88871AP ( mode 0 ) /lact[3] /lact[2] /lact[1] /lact[0] /lact[5] /lact[4] /lact[6] /lact[7] /lpart[7] /lpart[6] /lpart[5] /lpart[4] /lpart[3] /lpart[2] /lpart[1] /lpart[0] /luti[4] /luti[5] /luti[3] /luti[2] /luti[1] /luti[0] /lcol10 /lsel10 vdd mclk nc nc nc nc nc nc nc nc col[0] col[1] col[2] col[3] col[4] /lcol100 mdo mdc 96 col[5] col[6] col[7]
AX88871AP bripeater asix electronics corporation 8 1.5 pin connection diagram (mode 1) fig - 3 pin connection diagram for mode 1 note : power on configuration setup signals refer section 2.6 cross referance table bma[12] bma[0] /hir_acti[1] txen[6] txer[5] rxer[4] txd[3][1] rxd[3][2] rxdv[2] vdd /hir_acto[4] vss /hir_acto[7] lclk vdd nc 166 186 190 200 123 118 122 143 140 149 78 70 64 54 41 32 24 12 8 bma[9] bma[4] /hir_acti[3] txd[7][1] rxd[6][1] txen[5] rxd[5][1] crs[4] txen[3] rxd[2][3] txer[0] /hir_acto[5] vss hird_odir vss vss1 171 174 192 203 206 117 151 148 75 57 42 26 31 21 mdc bma[1] /hir_acti[0] /hir_acti[5] rxclk[7] rxd[5][2] txd[4][3] rxd[3][3] rxdv[3] txer[2] crs[2] rxd[1][1] rxd[1][0] txd[1][0] led<1> 165 207 145 107 105 83 66 65 63 60 25 16 13 3 7 bma[5] bmd[3] rxd[6][2] txd[3][3] rxd[2][0] rxd[1][3] crs[1] rxd[0][0] vdd hird[0] /hird_v vss vdd1 159 187 195 196 197 131 128 115 112 134 61 33 bma[7] txd[7][2] rxd[7][0] rxd[6][0] crs[3] txd[0][0] vdd 170 198 111 132 139 136 156 154 99 91 43 19 15 4 bma[11] bma[14] bma[15] /half10 /hir_acti[4] /hir_acti[6] rxd[7][2] crs[7] rxclk[6] txd[5][3] rxd[5][3] txd[2][3] rxd[0][3] vss1 vdd1 vss 157 162 178 204 109 106 104 101 82 81 77 62 11 6 bma[8] bmd[4] rxd[7][3] txd[6][3] txd[5][1] rxd[4][3] txd[2][2] rxd[0][2] daisy_out test vss 208 142 155 147 94 89 71 49 17 txer[7] txer[6] rxclk[5] txen[4] txd[3][2] txer[3] txd[1][2] vdd1 176 144 138 95 90 68 58 56 55 45 23 bma[2] rxdv[7] rxer[6] rxd[5][0] txd[5][2] txd[4][1] txd[2][0] rxdv[1] led<2> 53 161 163 184 194 116 113 59 36 34 1 txd[6][1] txer[4] rxclk[3] rxd[3][0] rxd[1][2] txd[0][2] daisy_in hird_ck vdd 164 168 181 124 108 87 /hir_acti[2] rxdv[6] crs[6] rxd[4][2] rxdv[4] rxd[3][1] rxer[3] rxclk[2] rxer[1] txd[1][3] txd[1][1] txen[1] rxclk[0] /bma[15] /hir_acto[0] /hir_acto[1] hird[3] 167 172 130 141 100 98 85 28 22 9 /lcol100 bma[10] bma[3] bmd[1] /hir_acti[7] rxd[7][1] crs[5] rxd[4][0] rxclk[4] rxd[2][2] txen[2] rxer[0] txen[0] /hir_acto[6] vss vss1 vss /rst hird[1] vss 175 183 185 193 126 119 110 121 137 135 152 153 79 74 bma[16] bmd[5] col_o[7] txd[7][0] txd[5][0] txd[0][1] crs[0] hird[2] vdd vdd1 169 188 202 96 93 80 72 46 29 52 10 mdo /bmwr bma[6] rxer[2] rxclk[1] txd[0][3] /hir_acto[3] vss1 158 177 150 146 103 67 44 39 27 51 5 bmd[0] bmd[2] txen[7] col_o[6] txd[6][2] rxdv[5] led_ck /lcol10 182 199 201 127 125 120 114 92 73 69 38 48 bma[13] bmd[7] txd[7][3] txd[6][0] rxd[6][3] rxer[5] txd[3][0] vss vdd /hird_er 180 189 205 76 47 35 30 20 2 bma[17] bmd[6] rxer[7] txd[4][2] rxd[4][1] txd[4][0] txd[2][1] rxd[2][1] txer[1] rxdv[0] rxd[0][1] /hir_acto[2] led<0> 160 173 179 191 129 133 102 97 88 86 84 40 37 50 18 14 AX88871AP ( mode 1 ) vdd mclk col[0] col[1] col[2] col[3] col[4] col[5] col[6] col[7] /lir_act[3] /lir_act[2] /lir_act[1] /lir_act[0]
AX88871AP bripeater asix electronics corporation 9 2.0 pin description the following terms describe the ax88871a pinout: all pin names with the ? / ? suffix are asserted low. i = input o = output i/o = input /output 2.1 mii interfaces signal name type pin no. description txer[7:0] or col[7:0] o or i 89, 72, 56 40, 24, 9 202, 187 transmit error : when /half10 pin set to ? high ? . txer is transition synchronously with respect to the rising edge of txclk . asserted high when a code violation is request to be send collision : when /half10 pin set to ? low ? . col is input from phy, when 10mbps phy is in half-duplex mode. txd[7:0][3:0] o 88-85, 70-67 55-52, 39-36 23-20, 8-5 201-198 186-185 182-181 transmit data : txd[3:0] is transition synchronously with respect to the rising edge of txclk. for each txclk period in which txen is asserted, txd[3:0] are accepted for transmission by the phy. txen[7:0] o 84, 66,51 35, 19, 4 197, 180 transmit enable : txen is transition synchronously with respect to the rising edge of txclk. txen indicates that the port is presenting nibbles on txd [3:0] for transmission. rxd[7:0][3:0] i 83-80, 65-62 49-46, 34-31 18-15, 3-2 208-207 195-192 179-176 receive data : rxd [3:0] is driven by the phy synchronously with respect to rxclk. rxer[7:0] i 74, 57, 42 27, 11, 203, 188, 172 receive error : rxer ,is driven by phy and synchronous to rxclk, is asserted for one or more rxclk periods to indicate to the port that an error has detected. rxclk[7:0] i 79, 61, 45 30, 14, 206, 191, 175 receive clock : rx_clk is a continuous clock that provides the timing reference for the transfer of the rxdv,rxd [3:0] and rxer signals from the phy to the mii port of the repeater. rxdv[7:0] i 75, 58, 43 28, 12, 204, 189, 173 receive data valid : rx_dv is driven by the phy synchronously with respect to rxclk. asserted high when valid data is present on rxd [3:0]. crs[7:0] i 76, 59, 44, 29, 13, 205, 190, 174 carrier sense : asynchronous signal crs is asserted by the phy when receive medium is non-idle at full duplex mode. col_o[6] o 73 collision : collision detection signal for port 6 col_o[7] o 90 collision : collision detection signal for port 7
AX88871AP bripeater asix electronics corporation 10 2.2 expansion bus interface for 100 mbps signal name type pin no. description hird[3:0] or /lact[3:0] i/o/z /pu 165-162 inter repeater data : when mode= ? 1 ? , nibble data input/output. transfer data from the ? active ? ax88871a to all other ? inactive ? ax88871as. the bus-master of the ird bus is determined by ir_vect bus arbitration. /lact[3:0] : when mode= ? 0 ? , those pins drive activity[3:0] leds directly. /hird_v or /lact[4] i/o/z /pu 159 inter repeater data valid : when mode= ? 1 ? , this signal reflect the rx_dv status of the active port across the inter repeater bus. used to frame good packets. /lact[4] : when mode= ? 0 ? , this pin drives port 4 activity led directly. /hird_er or /lact[5] i/o/z /pu 160 inter repeater data error: when mode= ? 1 ? , this signal reflect the rx_er status of the active port across the inter repeater bus. used to track receive errors from the phy in real time. /lact[5] : when mode= ? 0 ? , this pin drives port 5 activity led directly. hird_ck or /lact[6] i/o/z /pu 158 inter repeater clock valid : when mode= ? 1 ? , all inter repeater signals are synchronized to the rising edge of this clock. /lact[6] : when mode= ? 0 ? , this pin drives port 6 activity led directly. hird_odir or /lact[7] o 157 inter repeater data in/out direction : when mode= ? 1 ? , this pin indicates the direction of data for external transceiver. ? high ? = ird[3:0], /ird_er, /ird_v , ird_ck are output. ? low ? = ird[3:0], /ird_er, /ird_v , ird_ck are input. /lact[7] : when mode= ? 0 ? , this pin drives port 7 activity led directly. /hir_acto[5:0] or /lpart[5:0] i/o/oc 153-148 inter repeater activity in/out: when mode= ? 1 ? , the local repeater activity appearance, the signal of the related rid (repeater id) will be asserted and as a output pin. all other pins serve as input pins but except the collision conditions. when collision occurred , the signal of related (rid-1) pins will also served as outputs and will active during local collision period. the exception case is when rid = 0, then (rid-1) is replaced with (rid+1). /lpart[5:0] : when mode= ? 0 ? , those pins drive partition[5:0] leds directly. /hir_acto[7:6] or /lir_act[3:2] or /lpart[7:6] i/o/oc 155-1154 inter repeater activity in/out: when mode = ? 1 ? and stack = ? 1 ? the function is the same as /hir_acto[5:0]. local repeater activity in/ out : when mode = ? 1 ? and stack = ? 0 ? the function is the same as /hir_acto[5:0] but for local repeater activity only. /lpart[7:6] : when mode= ? 0 ? , those pins drive partition[7:6] leds directly. /hir_acti[5:0] or nc[5:0] i/pu 144-139 inter repeater activity in: these pins perform the same function as /ir_ acto[7:0] when they serve as input function. then the /ir_ acto[7:0] insert external buffers the input function must be replaced with /ir_acti [7:0]. nc : when mode= ? 0 ? , those pins keep no connection. /hir_acti[7:6] or /lir_act[1:0] or nc[7:0] i/o/pu 146-145 inter repeater activity in : when mode = ? 1 ? and stack = ? 1 ? the function is the same as /hir_acti[5:0]. local repeater activity in/ out : when mode = ? 1 ? and stack = ? 0 ? the function is the same as /hir_acto[5:0] but for local repeater activity only. nc : when mode= ? 0 ? , those pins keep no connection.
AX88871AP bripeater asix electronics corporation 11 2.3 led display signal name type pin no. description led[2:0] or /luti[2:0] o 100-98 led display information : when mode= ? 1 ? , those signals indicate each port ? s partition, jabber, activity, collision (global), repeater id, utilization % (global), collision % (global) in sequence. for detail , see the led timing specification /luti[2:0] : when mode= ? 0 ? , those pins drive utilization[2:0] leds directly. the utilization % display define as following : (see note 1 also) the collision % display define as following : led_ck or /luti[3] o 101 led clock signal : when mode= ? 1 ? , the signal is a discontinue clock for led signals serial shift out. the clock period width is 40ns and last 16 cycle with every 125ms repeated. /luti[3] : when mode= ? 0 ? , this pin drive utilization[3] led directly. /lcol10 or /luti[4] o/z 138 collision led for 10mbps : when mode= ? 1 ? , this pin indicates 10mbps repeater collision occurred. /luti[4] : when mode= ? 0 ? , this pin drive utilization[4] led directly. nc or /luti[5] o 137 nc : when mode= ? 1 ? , the pin function is reserved. /luti[5] : when mode= ? 0 ? , this pin drive utilization[5] led directly. /lcol100 o/z 93 collision led for 100mbps : this pin indicates 100mbps repeater collision occurred. collision % led0 led1 led2 led3 led4 led5 led6 led7 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 2 0 0 1 1 1 1 1 1 5 0 0 0 1 1 1 1 1 10 0 0 0 0 1 1 1 1 15 0 0 0 0 0 1 1 1 20 0 0 0 0 0 0 1 1 30 0 0 0 0 0 0 0 1 60+ 0 0 0 0 0 0 0 0 utilization % led0 led1 led2 led3 led4 led5 led6 led7 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 5 0 0 1 1 1 1 1 1 10 0 0 0 1 1 1 1 1 15 0 0 0 0 1 1 1 1 30 0 0 0 0 0 1 1 1 40 0 0 0 0 0 0 1 1 60 0 0 0 0 0 0 0 1 80+ 0 0 0 0 0 0 0 0
AX88871AP bripeater asix electronics corporation 12 note : the utilization % display define as following for mode 0 led direct driving. note 1 : the calculation formulas of traffic utilization between asix and netcom is difference, so you will get different results when using smartbit (sb) testing this item. we found the smartbit calculate the utilization without include 96 bit time inter frame gap. so the utilization value can be 100%. as well as we found sb used min packet size (64 byte) and min ifg (96 bit-time) as 100% utilization. in theory, when max packet size(1518 byte) and min ifg the utilization will be more than 100%, but sb also treat it as 100%. in our ax88871 design, we use real cable bandwidth as calculation base. we calculate the bit counts of carrier within a unit time. because of the existence of inter frame gap, in our calculation 100% utilization is impossible. so the above two cases (64 byte packet size and 1518 byte packet size with min. ifg ), we will count as 85.7% and 99.2%. if using sb test result to indicate utilization led the value must be modified. see the following reference table. asix ? s utilization% 1 5 10 15 30 60 smartbit ? s utilization% 2 7 12 17 34 68 2.4 buffer memory pins group signal name type pin no. description bma[17:0] o 113-106, 104, 103, 132-129, 127, 124 b uffer address bus. bmd[7:0] i/o 122-115 b uffer data bus . /bmwr i/o 102 m emory control pin for write. /bma[15] i/o 97 invert b uffer address 15. utilization % /luti0 /luti1 /luti2 /luti3 /luti4 /luti5 0 1 1 1 1 1 1 1 0 1 1 1 1 1 5 0 0 1 1 1 1 10 0 0 0 1 1 1 15 0 0 0 0 1 1 30 0 0 0 0 0 1 60 0 0 0 0 0 0
AX88871AP bripeater asix electronics corporation 13 2.5 miscellaneous signal name type pin no. description lclk i 169 local clock : must be run at 25mhz . used for transmit data to phy devices, /rst i 167 reset : the chip is reset when this signal is asserted low. daisy_in or /lsel10 i/pu 135 repeater identification number daisy-chain in : when mode= ? 1 ? , this pin is a daisy chain serial input for repeater id. a state machine always monitor the input if a correct data (rid) present at the pin, the (rid+1) will be written to rid register and override the power on setup rid for the chip. /lsel10 : when mode= ? 0 ? , this pin select 10mbps global led status ( utilization (%) and collision (%) ) when ? low ? ; otherwise , 100mbps led status is selected. daisy_out or /lcol10 o/ml 136 repeater identification number daisy-chain out : when mode= ? 1 ? , this pin is periodically shift out the rid of itself to the next chained chip to inform that this id has already been occupied. the rid is shift out periodically every about 200us. /lcol : when mode= ? 0 ? , this pin drives 10mbps collision led directly. mclk o 96 mii clock out : 2.5mhz 10mbps mii reference clock mdo o 95 station management data out : for setup phy auto-negotiation registers. a burst write commands are issue to setup phy register after reset. the phy address 4h, 5h, 6h, 7h, 8h, 9h,ah and bh will be written as register 4h to value 00a1h ( advertise register set to 10/100 half-duplex mode)and register 0h to value 1000h(enable auto-negotiation). mdc o 94 station management data clock out : for mdo reference clock. test i/pd 166 test pin : the pin is just for test mode setting purpose only. must be pull low when normal operation. /half10 i/pu 170 half-duplex mode in 10mbps : pull low with 10k ohm resister for 10mbps phy in half-duplex mode. vdd i 1, 25, 50, 71, 78, 92 105, 128, 134, 161, 171, 183 power : +5v +/-5% vss i 10, 26, 41 60, 77, 91, 114, 123, 133, 147, 156, 168, 184, 196 power: 0v
AX88871AP bripeater asix electronics corporation 14 2.6 power on configuration setup signals cross reference table signal name share with description opt[6] col_o[6] opt[6] : option for external device type to connect to port 6. default ? high ? is for phy type device. otherwise, ? low ? for bridge, switch or mac type device. opt[7] col_o[7] opt[7] : option for external device type to connect to port 7. default ? high ? is for phy type device. otherwise, ? low ? for bridge, switch or mac type device. opt[0] txen7 opt[0] : option for led display. default ? high ? for normal operation. user may pull the pin ? low ? with 10k ohm resister to force 10m or 100m led disable when all the ports are the same speed condition. opt[1] txd[5][3] opt[1] : option for partition schime. default ? high ? for normal operation. user may pull the pin ? low ? with 10k ohm resister to force hardly enter partition state. txm_mode txd[6][3] txm_ mode : option for internal used. default ? high ? user may pull the pin ? low ? with 10k ohm resister for reserve transmition mode alternaty. mode txd[6][2] mode = 0 : single chip repeater application. mode = 1 : multiple chips cascaded repeater application. opt[3] txd[6][1] opt[3] : option for internal used. please keep the pin with default value. en_flow_ctl txd[6][0] en_flow_ctl = 0 : disable flow control function. en_flow_ctl = 1 : enable flow control function. st_fw txd[7][3] st_ fw : default ? high ? for store and forward mode. user may pull the pin ? low ? with 10k ohm resister to seting to fragment free mode. entries txd[7][2] entries = 0 : 1024 entries supported entries = 1 : 256 entries supported mem_size[1] mem_size[0] txd[7][1] txd[7][0] mem_size[1] mem_size[0] size (k) 1 1 32k 1 0 64k 0 1 128k 0 0 256k /ir_act_en /bmwr inter repeater active input pin enable : this input active low to enable /hir_acti[7:0] pins as inter-repeater carrier sense detection input. otherwise, /hir_ acti[7:0] pins are disabled. the setup works only in mode = 1. /dis_daisy /bma[15] /dis_ daisy : default pull-up to enable daisy chain function. to disable daisy chain function pull the pin down external. stack txd[5][2] stack option : default is level one using the legacy expansion method to cascade 8 repeater chips. when pull the pin low with 10k ohm resister, using inter-repeater bus horizontally cascades 4 ax88771s and vertically cascades 6 repeaters maximum up-to 192 ports can be constructed. lrid[1] txd[5][1] local repeater identification number lrid[1]: when power on reset this pin as inputs to setup the local repeater id of the chip. lrid[1:0] indicate the local repeater id from 0 to 3. lrid[0] txd[5][0] local repeater identification number lrid[0]: when power on reset this pin as inputs to setup the local repeater id of the chip. lrid[1:0] indicate the local repeater id from 0 to 3. rid[2] mclk repeater identification number rid[2]: when power on reset this pin as inputs to setup the repeater id of the chip. rid[2:0] indicate the repeater id from 0 to 7. rid[1] mdo repeater identification number rid[1]: when power on reset this pin as inputs to setup the repeater id of the chip. rid[2:0] indicate the repeater id from 0 to 7. rid[0] mdc repeater identification number rid[0]: when power on reset this pin as inputs to setup the repeater id of the chip. rid[2:0] indicate the repeater id from 0 to 7. all of the above signals are pull-up for default values.
AX88871AP bripeater asix electronics corporation 15 3.0 functional description blank now fig - 4 functional block diagram
AX88871AP bripeater asix electronics corporation 16 3.1 repeater state machine the repeater state machine is used to control repeater behavior , generates right signal in corresponding states. the repeater state machine is in idle state when there is no carrier presented on any ports . when there is only one port has receive activity, the repeater state machine will enter data - forwarding state to ensure correct data forwarding to other connected ports. if collision happens anytime , the repeater state machine detects collision then send jam pattern to all ports until collision ceases. idle state the idle state happens when these conditions exists: a. /rst is low. b. all crs[7:0] and dcrs are not asserted high in single chip application. c. repeater sense no inter repeater active signal in cascade application, that is, all /ir_ acto[7:0] remains high. data forwarding state the state happens when these conditions exists: a. only one signal asserted among crs[7:0] and dcrs in single chip application. b. only one of ir_acto[7:0] become low if in cascade application. the repeater state machine stores receiving packet and transmits to all other ports except for 1. the port is jabbered. 2. the port is isolated. collision state the collision state happens when these conditions exists: a. there are two or more signals asserted high among crs[7:0] and dcrs in single chip system. b. there are two or more signals asserted low among /ir_ acto[7:0] in cascade system. c. only one carrier exists but rxdv still low exceeds 4 clock cycles .the repeater sends collision pattern to all ports. one port left state the state happens only when there is no collision but still one port which experienced collision has receive activity. the repeater remains send collision pattern to all ports except the port. 3.2 rxe /txe control idle state the repeater sends no data to any port. rxe(all) = 0, rxe_ir = 0. txe(all) = 0, txe_ir = 0. data forwarding state if active(x) = 1, x is the local connected port, rxe(x) = 1, rxe(all-x) = 0, rxe_ir = 0. txe(x) = 0, txe(all-x) = 1, txe_ir = 1. if active(x) = 1, x is the inter repeater port, rxe(all) = 0, rxe_ir =1. txe(all) = 1, txe_ir = 0. collision state the repeater sends jam pattern to all ports. rxe(all) = 0, rxe_ir = 0. txe(all) = 1, txe_ir = 0. one port left state
AX88871AP bripeater asix electronics corporation 17 the repeater sends jam pattern to all other port except for the still activity port. rxe(all) = 0, rxe_ir = 0. txe(all-x) = 1, txe_ir = 0. suppose x is the one left port. 3.3 jabber state machine to prevent an illegally long reception of data from reaching the repeater unit, each port has its own jabber timer. if a reception exceeds this duration (64k bit times for ax88871a) , the jabber condition will be detected. in this condition, repeater unit will disable receive and transmit packets for the jabbered port and the other ports remain the normal operation. when the carrier is no longer detected for the jabbered port or reset the repeater, the jabber function will be clear and re-enable reception and transmission. 3.4 partition state machine the partition state machine is used to protect network from being upset when a port suffer continuous collision, each port uses a partition state machine to detect and prevent this condition. when a port suffer from continuous 64 times of collision events, then it goes to partition state. the partitioned port will be not released until a packet without collision be transmitted( more than 512 bit times for ax88871a) or reset the repeater. 3.5 expansion logic(cascade interface) the expansion logic is used to stack numerous repeaters to expend the number of connected ports. the expansion logic can be divided into two types: expansion logic without buffer (minimum mode) in this mode, use /ir_ acto[7:0] to cascade repeaters in back plane. just connect /ir_ acto[7:0] of all repeaters without using buffer. this mode is supposed to cascade repeaters on the same board. in this application, the stackable system can reach to 4 repeaters. expansion logic with buffer (maximum mode) this mode is entered with the setting of /dis_dmii = 0, the dedicated port isn ? t existed again in this mode. now the dedicated pins drxd[3:0], dcrs, drx_dv, drx_er, drx_clk play a role as ir_acti[7:0]. use /ir_ acto[7:0] and /ir_acti[7:0] to cascade repeaters in back plane. buffers are used both in /ir_ acto[7:0] and /ir_acti[7:0]. the mode is supposed to cascade repeaters on different boards via cables. in this application, the stackable system can reach to 8 repeaters. /ir_acto<7:0> are driven according to repeater id and receive activity of local connected ports as follows: repeater id idle state only one port activity more than one port activity 000 11111111 11111110 11111100 001 11111111 11111101 11111100 010 11111111 11111011 11111001 011 11111111 11110111 11110011 100 11111111 11101111 11100111 101 11111111 11011111 11001111 110 11111111 10111111 10011111 111 11111111 01111111 00111111 note: all /ir_ acto[7:0] will be in open-drain status when they aren ? t driven. these signals present high via external pull high resister. 3.6 data flow control
AX88871AP bripeater asix electronics corporation 18 the signals on the ir bus (such as ird[3:0], ird_v_n, ird_er_n, ird_ck) flow either into or out of the repeater depending upon the repeater ? s state. only if the repeater receive packet from local port without collision occurs, the ir signals flow out of repeater. otherwise, these ir signals flow into repeater. in cascade system, it must guarantee that only one repeater drives these signals to avoid contention. 3.7 rid receive-transmit interface(daisy chain logic) in the cascade system, repeater id of each chip will be re-arranged by serial in/serial out daisy chain logic. the logic use daisy_in pin to monitor the rid value of the previous chained chip, and override the original id of the current chip with the value of (rid+1) . use the daisy_out pin to periodically (about 200us) send out the exact rid of the current chip to inform the next chained chip. by this way , each repeater chip in 8 ax88871a stackable application will keep unique id of itself. the rid is used in inter repeater bus arbitration. daisy_in/out frame format idle start bit data0 data1 data2 data3 1 0 rid[0] rid[1] rid[2] parity notes: parity = 1 when sum of 1 ? s in rid[2:0] is even if no daisy-chain input, that is, daisy_in keep high , the rid of current chip can be clear to 0 during time out period. the timer for time out is about 4sec. there are a input setting , /dis_daisy, which enable/disable daisy-chain function. with the low setting , the rid of current chip don ? t care the present data on daisy_in and can ? t be overrided. 3.8 led display interface ax88871a provides per-port led status indication for partition , jabber, activity and support rate - based led for global partition and collision, utilization (%) for 10/100mbps. .detail function is described on the previous pin description(led interface). led[2:0] are all active low. there are two display ways : complicated and simple way. it depends on the setting of mode. multiple chips cascaded application (mode = 1) led[2:0] status driver wave-form as follows : jab7 jab6 jab5 jab4 jab3 jab2 jab1 jab0 part 7 part 6 led_ck led[0] '0' rid2 rid1 rid0 100m gcol 10m gcol led[1] led[2] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d12 d13 d14 d10 d15 part 0 part 1 part 2 part 3 part 4 part 5 act0 act1 act2 act3 act4 act5 act6 act7 10m uti7 10m uti0 10m uti1 10m uti2 10m uti3 10m uti4 10m uti5 10m uti6 100m uti7 100m uti0 100m uti2 100m uti3 100m uti4 100m uti5 100m uti6 100m uti1 g part ram fail
AX88871AP bripeater asix electronics corporation 19 notes: a. part7~0indicates partition status for each port b. jab7~0 indicates jabber status for each port c. act7~0 indicates activity status for each port d. rid2~0 is the id of repeater chip e. 10m uti7~0 indicate global utilization rate of f. 100m uti7~0 indicate global utilization rate of 10mbps for each 104.8ms sampling period. 100mbps for each 104.8ms sampling period. g. 10m gcol indicate global collision h. 100m gcol indicate global collision i. gpart : indicate global partition. j. ram fail : bridge ram test fail. it must use external shift register to decode data on led[2:0]. the application shows as follows: 74ls164(#1) 74ls164(#2) q q q q q q q q d d q q q q q q q q part0 part1 part2 part3 part4 part5 part6 part7 jab0 jab1 jab2 jab3 jab4 jab5 jab6 jab7 led[0] led_ck fig - 5 application for led display if the user don ? t want to show jabber status, take away the latter 74ls164(#2). the application is the same for led[2:1]. single chip application (mode=0) in this mode, the inter repeater pins are not useful, these pin can be used for display led status directly. then the led application become simple. dump signal dump signal dump signal /hir_acto[0] /part[0] hird[0] /act[0] led[0] /uti[0] /hir_acto[1] /part[1] hird[1] /act[1] led[1] /uti[1] /hir_acto[2] /part[2] hird[2] /act[2] led[2] /uti[2] /hir_acto[3] /part[3] hird[3] /act[3] led_ck /uti[3] /hir_acto[4] /part[4] /hird_v /act[4] hmd /uti[4] /hir_acto[5] /part[5] /hird_er /act[5] htx_rdy /uti[5] /hir_acto[6] /part[6] hird_ck /act[6] daisy_out /lcol10 /hir_acto[7] /part[7] hird_odir /act[7] /lcol100 /lcol100
AX88871AP bripeater asix electronics corporation 20 4.0 internal registers 4.1 configuration register (config) bit bit name access bit description d14 /half10 r/w half-duplex mode in 10mbps : ? low ? resister to 10mbps phy in half- duplex mode. ? high ? resister to 10mbps phy in full-duplex mode. d13 opt[0] r/w opt[0] : option for led display. default ? high ? for normal operation. user may pull the pin ? low ? with 10k ohm resister to force 10m or 100m led disable when all the ports are the same speed condition. d12 opt[1] r/w opt[1] : option for partition schime. default ? high ? for normal operation. user may pull the pin ? low ? with 10k ohm resister to force hardly enter partition state. d11 txm_mode r/w txm_ mode : option for internal used. default ? high ? user may pull the pin ? low ? with 10k ohm resister for reserve transmition mode alternaty. d10 opt[3] r/w opt[3] : option for internal used. please keep the pin with default value. d9 opt[4] r/w opt[4] : no used. d8 opt[6] r/w opt[6] : option for external device type to connect to port 6. default ? high ? is for phy type device. otherwise, ? low ? for bridge, switch or mac type device. d7 opt[7] r/w opt[7] : option for external device type to connect to port 7. default ? high ? is for phy type device. otherwise, ? low ? for bridge, switch or mac type device. d6 mode r/w mode = 0 : single chip repeater application. mode = 1 : multiple chips cascaded repeater application. d5 st_fw r/w st_fw = 0 : fragment-free mode st_fw =1 : store-n-forward mode d4 entries r/w entries = 0 : 1024 entries supported entries = 1 : 256 entries supported d3-2 mem_size[1] mem_size[0] r/w mem_size[1] mem_size[1] size (k) 1 1 32k 1 0 64k 0 1 128k 0 0 256k d1 /ir_act_en r/w inter repeater active input pin enable : this input active low to enable /hir_acti[7:0] pins as inter-repeater carrier sense detection input. otherwise, /hir_ acti[7:0] pins are disabled. d0 /dis_daisy r/w /dis_ daisy : default pull-up to enable daisy chain function. to disable daisy chain function pull the pin down external. 4.2 repeater id register bit bit name access bit description d2-d0 rid[2:0] r/w repeater id : at the rising edge of /rst , the value of rid[2:0] are latched in this register as d[2:0]. the setting of rid[2:0]can be override according to the data from serial daisy-chain daisy_in pin input . note that in system application, the maximum of 8 devices can be cascade.
AX88871AP bripeater asix electronics corporation 21 5.0 electrical specification and timing 5.1 absolute maximum ratings description sym min max units operating temperature ta 0 +70 c storage temperature ts -55 +150 c supply voltage vcc -0.5 +7 v input voltage vin vss-0.5 vdd+0.5 v output voltage vout vss-0.5 vdd+0.5 v lead temperature (soldering 10 seconds maximum) tl -55 +235 c note : stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability 5.2 general operation conditions description sym min max units operating temperature ta 0 +70 c supply voltage vdd +4.75 +5.25 v 5.3 dc characteristics (vdd=4.75v to 5.25v, vss=0v, ta=0 c to 70 c) description sym min max units low input voltage vil vss-0.5 0.8 v high input voltage vih 2 vdd+0.5 v low output voltage vol 0.4 v high output voltage voh 2.4 v input leakage current 1 (note 1) iil1 10 ua input leakage current 2 (note 2) iil1 500 ua output leakage current iol 10 ua description sym min tpy max units power consumption pc 180 240 ma note : 1. all the input pins without pull low or pull high. 2. those pins had been pull low or pull high.
AX88871AP bripeater asix electronics corporation 22 5.4 ac specifications 5.4.1 mii interface timing tx & rx t0 t1 lclk t2 t2 tx_en t3 t3 tx_er txd symbol description min typ. max units t0 local clock cycle time 39.996 40 40.004 ns t1 local clock high time 14 20 26 ns t2 tx_en delay from lclk high 7.440 21.760 ns t3 tx_er or txd delay from lclk high 3.410 13.320 ns t4 t5 rx_clk crs t6 t7 rxe t8 rxdv t9 rxd rxer
AX88871AP bripeater asix electronics corporation 23 symbol description min typ. max units t4 rx_clk clock cycle time 39.996 40 40.004 ns t5 rx_clk clock high time 14 20 26 ns t6 crs to rxe assertion delay 20 ns t7 crs to rxe de-assertion delay 160 200 ns t8 crs to rxdv delay requirement 40 160 ns t9 rxd or rxdv or rx_er setup to rx_clk rise time 10 - ns 5.4.2 expansion bus crs t1 t2 hird-odir hird_ck t3 hird[3:0] t4 /hird_er t5 t6 /hird_v symbol description min max units t1 crs assertion to hird-odir assertion - 20 ns t2 crs de-assertion to hird-odir de-assertion 160 200 ns t3 hird[3:0] setup time to hird-ck high 10 - ns t4 /hird_er setup time to hird-ck high 10 - ns t5 /hird_v setup time to hird-ck high 5 - ns t6 /hird_v hold time from hird-ck high 5 - ns
AX88871AP bripeater asix electronics corporation 24 5.4.3 sram read cycle and write cycle bma[18:0] /bmwr bmd[7:0] symbol description min max units t1 read cycle time 40 - ns t2 bmd[7:0] setup time 3 - ns t3 bmd[7:0] hold time 3 - ns ba[18:0] /bmwr bd[7:0] symbol description min max units t4 write cycle time 38 - ns t5 write pulse wtdth 20 - ns t6 bmd[7:0] data valid to end of write 14 - ns t7 bmd[7:0] data hold from end of write 1 ns t1 t3 t2 t4 t7 t5 t6
AX88871AP bripeater asix electronics corporation 25 5.4.4 led display t3 led_ck -------- - ~ ~ ------- d0 d1 d2 .............. d14 d15 d0 d1 d2 t4 t3 led_ck t1 t2 led[2:0] d0 d1 d2 d3 ------- d15 d0 symbol description min typ. max units t1 led setup to led_ck high 190 200 ns t2 led hold from led_ck high 200 210 ns t3 led_ck period width 400 ns t4 continuous 16 led_ck cycle time 52.4 ms 5.4.5 led display after reset /reset t1 t2 t2 t2 t3 led[2:0] symbol description min typ. max units t1 repeater reset time 1000 ns t2 led blink time after reset 838.4 ms t3 led dark time before normal display 419.2 ms
AX88871AP bripeater asix electronics corporation 26 5.4.6 repeater id daisy chain t1 t2 t2 daisy- out id0 id1 id2 id0 id1 id2 t3 daisy- in id0 id1 id2 id0 id1 id2 symbol description min typ. max units t1 daisy chain one burst period 204.8 us t2 start bit period or data width 12.8 us t3 time-out occur when no data present on daisy_in * 3.8 s note : daisy-chain data-in time-out stands for no input data (always high level) for the specific time.
AX88871AP bripeater asix electronics corporation 27 6.0 package information b e d hd e he pin 1 a2 a1 l l1 q milimeter symbol min. nom max a1 0.05 0.25 0.5 a2 3.17 3.32 3.47 b 0.10 0.20 0.30 d 27.90 28.00 28.10 e 27.90 28.00 28.10 e 0.50 hd 30.35 30.60 30.85 he 30.35 30.60 30.85 l 0.45 0.60 0.75 l1 1.30 q 0 10
AX88871AP bripeater asix electronics corporation 28 appendix a : applications two type of applications for ax88871a are illustrated bellow. a.1 stand-along 8-ports 10/100mbps hub application fig - 6 stand-along 8-ports 10/100mbps hub application a.2 multiple stand-along hub cascade application (old stack scheme) ? ? ? ? ? ? ? ? ? ? ? .. fig - 7 multiple stand-along hub cascade application with old cascade method ax88871a bripeater controller mii interface mii interface quad mii transceiver 8 bits sram 100mbps cascade interface quad mii transceiver led array ax88871a #0 bripeater controller ax88871a #7 bripeater controller 8 bits sram 8 bits sram quad mii transceiver quad mii transceiver quad mii transceiver quad mii transceiver
AX88871AP bripeater asix electronics corporation 29 a.3 multiple stand-along hub cascade application (new stack scheme) fig - 8 multiple stand-along hub cascade application with new cascade method 100mbps horizontal cascade ax88871a #0 repeater controller ax88871a #3 repeater controller ax88871a #0 repeater controller ax88871a #3 repeater controller buffer buffer 100mbps horizontal cascade 100mbps vertical cascade hub #0 hub #5
AX88871AP bripeater asix electronics corporation 30 appendix b : using mii i/f connects to mac there are two ports of ax88871a can connect to mac type mii interface. for example, port 7 is illustrated bellow. 10k gnd ax88871 / repeater ax88195 / mac note : 1. the mac needs to run at halfduplex mode. 2. care must be taken that the receive side has enough setup and/or hold time 3. some kind of cpu with embbeded mac can also refer to this example using mii interface to connect to 10mbps mac device application for ax88871a is illustrated bellow. 10k gnd ax88871 / repeater 10mbps mac col_o7 txen7 (lclk) txd7[3:0] txer7 crs7 rxdv7 rxclk7 rxd7[3:0] rxer7 col crs rx_dv rx_clk rxd[3:0] rx_er tx_en tx_clk txd[3:0] tx_er 25mhz clock col_o7 txen7 mclk txd7[3:0] txer7 crs7 rxdv7 rxclk7 rxd7[3:0] rxer7 col crs rx_dv rx_clk rxd[3:0] rx_er tx_en tx_clk txd[3:0] tx_er

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